Complex electronic systems, built from tens or hundreds of millions of transistors, have become nearly ubiquitous in modern-day life. The market drives ever-increasing demands for performance, advanced feature sets, system versatility, and a variety of other rapidly changing system requirements. This leads to ever decreasing product life cycles and thus also leads to ever-shorter product development design cycles. To handle such electronic system complexity, designers utilize many electronic tools to address the complexity and shortened design cycles. Even with modern electronic design automation (EDA) tools, it is very difficult for a human designer to fully comprehend many modern electronic systems, simply due to the enormous scale of the designs.
Logic systems can be described at a variety of levels of abstraction, from low-level transistor layouts to high-level description languages. Most designers describe and design their electronic systems at a high-level of abstraction using an IEEE Standard hardware description language (HDL) such as Verilog™, SystemVerilog™, or VHDL™. High-level HDL is easier for designers to understand, especially for large, complex systems, and can describe sprawling concepts that are difficult to grasp using a lower level of abstraction. The HDL description can be converted into any other level of abstraction that is helpful to the developers. For example, a high-level description can be converted to a logic-level description such as a register-transfer language (RTL), a gate-level (GL) description, a layout-level description, or a mask-level description. Each lower level of abstraction introduces more detail into the design description.
Many different graphical representations are used during a typical design cycle to help the designer create and debug the electronic system. During design, block diagrams, schematic diagrams, physical layouts, and the like, are all used in various ways to represent design data. During the latter design stages, when a circuit's functionality is verified by circuit simulation, the aforementioned views are, in many cases, either not convenient or not available at all. The input data to a circuit simulator is usually one or more text files containing a hierarchical description of the circuit (i.e. a netlist) in a specific standard format optimized for the specific type of simulation to be run. Such formats are not optimized for human readability, and can be quite difficult for a human designer to understand. The output of a circuit simulation includes voltages and current data corresponding to circuit nodes and devices. Relating the output of the circuit simulation to the design data can be important in many situations. When only the netlist is available as the representation of the design data, legacy systems do not have a way to display the data in a way that is easy for a human to understand.